In Japanese Patent Application Laid-Open Publication No. 2006-19341 (Patent Document 1), a technique is described in which a semiconductor chip is embedded in a multilayer substrate including a resin layer and surface roughness of a back surface of the semiconductor chip is roughened.
In Japanese Patent Application Laid-Open Publication No. 2003-163240 (Patent Document 2), a technique of embedding a semiconductor chip among a plurality of substrates is described.